The present invention concerns a semiconductor memory device with means for preventing standby current and cell data, wherein input and output signal are stored and read through an input/output pad electrically connected with the n.sup.+ impurity doped region of the semiconductor substrate. The present application is based upon Korean Application No. 96-29030, which is incorporated herein by reference.
Recently, as semiconductor memory devices have been developed to have a high operational speed, undershoot is generated in an input/output signal. This causes an unwanted current to flow through the n.sup.+ impurity doped region connected with the input/output pad while being diffused or drifted into the memory cell arrays of the device.
Unfortunately, this unwanted injection of electrons into the n.sup.+ region can destroy the memory cell data.
FIG. 1 is a cross sectional view illustrating a first conventional semiconductor memory device. As shown in FIG. 1, a first p-type well 102, an n-type well 103, and a second p-type well 104 are each formed on different portions of a p-type semiconductor substrate 101. A first n.sup.+ doped impurity region 105 is embedded in the first p-type well 102 and is connected with an input/output pad 110. A second n.sup.+ impurity doped region 106 and a p.sup.+ impurity doped region 107 are embedded in the first p-type well 102, separate from the n.sup.+ impurity doped region 105. Both the second n.sup.+ impurity doped region 106 and the p.sup.+ impurity doped region 107 are connected with ground voltage V.sub.SS.
A third n.sup.+ impurity doped region 108 is embedded in the n-type well 103 and is connected to a source voltage V.sub.CC. A fourth embedded n.sup.+ impurity doped region 109 is embedded in the second p-type well 104 and is connected with the cell node.
In the conventional memory device shown above, when undershoot is generated due to the swing of the input/output signal inputting to the input/output pad 110, the diode of the first p-type well 102 is grounded and the first n.sup.+ impurity doped region 105 connected to the input/output pad 110 is forward biased.
FIG. 2 is a view illustrating an equivalent circuit of the semiconductor memory device of FIG. 1. As shown in FIG. 2, a forward bias is applied to the impurity doped region connected with the p-type semiconductor substrate 101 and the cell node. Thus, a part of the electrons injected from the first n.sup.+ impurity doped region 105 into the first p-type well 102 is transferred through the second n.sup.+ region 106 and the p.sup.+ region 107 to ground (path 100A in FIGS. 1 and 2). Most electrons are actually diffused into the p-type semiconductor substrate 101. Some of the electrons are is discharged through the n-type well 103 connected with the source voltage V.sub.CC (path 100B in FIGS. 1 and 2). The remaining electrons flow into the memory cell array, however, thus changing the cell data (path 100C in FIGS. 1 and 2).
The drawbacks of the conventional memory device are caused by the current paths 100B and 100C. The electrons travelling along current path 100B through the n-type well 103 can cause an operational failure as a standby current I.sub.sb. The electrons travelling along current path 100C into the fourth n.sup.+ impurity doped region 110 can lower the voltage of the cell node and thus destroy the cell data.
FIG. 3 is a cross sectional view illustrating a second conventional semiconductor memory device. As shown in FIG. 3, a first p-type well 202, an n-type well 203, and a second p-type well 204 are each formed on different portions of a p-type semiconductor substrate 201. A first n.sup.+ doped impurity region 205 is embedded in the first p-type well 202 and is connected with an input/output pad 110. A second n.sup.+ impurity doped region 206 and a p.sup.+ impurity doped region 207 are embedded in the first p-type well 202, separate from the n.sup.+ impurity doped region 205. Both the second n.sup.+ impurity doped region 206 and the p.sup.+ impurity doped region 207 are connected with ground voltage V.sub.SS.
A third n.sup.+ impurity doped region 208 is embedded in the n-type well 203 and is connected to a source voltage V.sub.CC. A fourth embedded n.sup.+ impurity doped region 209 is embedded in the second p-type well 204 and is connected with the cell node.
The semiconductor memory device of FIG. 3 differs from the semiconductor device of FIG. 1 in that the n-type well 203 extends under the first p-type well 202 to insulate the first p-type well from the p-type substrate 201. In this way, the n-type well 203 acts to protect the device from electrostatic charges by reducing the current path 200C from the input/output pad 110 to the cell node. Thus the current 200C in the second conventional semiconductor memory device is less than the current 100C in the first conventional semiconductor memory device.
FIG. 4 is a view illustrating an equivalent circuit of the semiconductor memory device as shown in FIG. 3. As shown in FIGS. 3 and 4, the current path 200C allows unwanted electrons to pass to the cell node and may cause a loss of data. However, in this device, the n-type well 203 and the first p-type well 202 are turned off in a reversely biased state, which blocks the flow of the electrons from the input/output pad to the cell node, minimizing the current along current path 100C. Thus, when undershoot is generated in an input/output signal entering the input/output pad 110, the diode of the first n.sup.+ impurity doped region 205 in the first p-type well 202 is forward biased, causing most electrons to flow into the first p-type well 202. A part of the electrons flowing into the first p-type well 202 is discharged through the path 200A to ground, but most of the remaining electrons flow into the n-type well 203 along current path 200B, i.e., as standby current I.sub.sb. Since the n-type well 203 and the p-type semiconductor substrate 201 are at this point reversely biased, the electrons are discharged to the source voltage V.sub.CC terminal through the path 200B instead of passing through the second p-type semiconductor substrate 204. This prevents a loss of data at the cell node and can reduce the standby current, I.sub.sb.